(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation self-aligned contacts to source/drain regions, next to polysilicon gate structures, that allows for xe2x80x9czeroxe2x80x9d spacing from contact structure to gate structure, without requiting the use of an insulating hard mask layer over the poly gate. The process is very useful for the xe2x80x9cstandardxe2x80x9d logic device salicided processes.
As transistor dimensions approached sub-micron, the conventional contact structures start to limit device performance in several ways. First, it becomes difficult to minimize contact resistance when the contact hole opening is of minimum size-and also problems with cleaning small contact holes become a concern. In addition, with defined conventional contacts, the area of the source/drain regions cannot be minimized because the contact hole has be aligned to these regions with a separate masking step, and a large xe2x80x9cextraxe2x80x9d area has to be allocated for possible misalignment. Furthermore, this larger xe2x80x9cextraxe2x80x9d area also results in increased source/drain-to-substrate junction capacitance, which impacts device speed. Finally, when conventional width MOSFET""s are fabricated with conventional contacts, several small, uniformly sized contact holes have to be used, rather than one wider contact hole. The main reason for this is that being of same size, the contact holes will to be opened simultaneously during the etching process. Using several small, equally sized contact holes rather than one wider one, wastes valuable space and the full width of the source/drain region is not fully utilize. Hence, the conventional device contact resistance is larger than it could have been in a device having minimum width. Self-aligned contact process schemes solve many of the micron and sub-micron CMOS MOSFET contact problems, easing both the device ground rule designs and easing the processing problems associated with convention contacts. The self-aligned contacts makes better use of the space and area over the source/drain region, as will be described in more detail.
In CMOS process technology, metal contacts for the source and drain electrical connection must have some distance or space away from the polysilicon gate to avoid electrically short circuiting the metal contact to the gate electrode. This spacing requirement restricts the product chip density in the design groundless, especially for memory chip technologies. The self-aligned process can be developed to allow xe2x80x9czeroxe2x80x9d spacing from the contact to source/drain to the gate. The standard or conventional self-aligned contact process utilizes a insulator capped polysilicon for the gate structure. The insulating layer, sometimes referred to as the xe2x80x9chard maskxe2x80x9d, can either be a conformal layer of silicon nitride or a conformal layer of silicon oxide. This standard SAC, self-aligned contact process works well for the Polycide process (Polycide structure: gate oxide/polysilicon gate/metal silicide) however, this process is not compatible with the Salicide process, self-aligned silicide due to the presence of the insulating layer over the poly gate. Therefore, in order to make the SAC process simple and compatible with the Salicide process, the a SAC process needs to be formulated without the use of the conventional conformal insulating layer over the polysilicon gate structure. As will be shown later in this invention, this invention describes a self-aligned source/drain contact process that allows for xe2x80x9czeroxe2x80x9d spacing between the source/drain contact to the gate, without requiring the use of an insulator layer on top of the polysilicon gate structure. As will be described later, the process described in this invention is completely compatible with both the state of-the-art current Salicide processing, as well as, the state of-the-art Polycide processing, with improved device electrical performance, improved design groundrules, and improved device reliability.
(2) Description of Related Art
In the fabrication of semiconductor integrated circuits the method of forming SAC, self-aligned contacts to. source/drain regions in the fabrication of CMOS MOSFET""s can be used to advantage to improve chip design ground rules, improve contact reliability, and improved device performance. In some cases, these self-aligned process schemes are merged with shallow trench isolation (STI) schemes. This section contains pertinent PRIOR ART patents and are meant to provide some processing background for the present invention.
U.S. Pat. No. 5,731,241 entitled xe2x80x9cSelf-Aligned Sacrificial oxide for Shallow Trench Isolationxe2x80x9d granted Mar. 24, 1998 to Jang et al describes a method of forming a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) ozone-TEOS tetra-ethyl-ortho-silicate layer over a trench oxide. This layer protects the trench oxide and is preferentially deposited over the trench oxide rather than over the thermally grown pad oxide. Two preferred embodiments are presented: (1) a first self aligned sacrificial ozone-TEOS layer over the trench before the pad oxide etch, and (2) a second self-aligned sacrificial ozone-TEOS layer deposited before the sacrificial ion implant oxide etch. The protecting ozone-TEOS film layer can be applied in a variety of process situations in shallow trench isolation (STI), where it protects the trench oxide from etch damage.
U.S. Pat. No. 5,817,562 entitled xe2x80x9cMethod for Making Improved Polysilicon FET Gate Electrode Structures and Sidewall Spacers for More Reliable Self-Aligned Contacts (SAC)xe2x80x9d granted Oct. 6, 1998 to Chang et al shows a method of forming FET stacked gate electrode structures with improved sidewall profiles. The more vertical sidewalls improve the control tolerance of the gate electrode effective length and improve the shape of the sidewall spacers for making more reliable metal contacts to self-aligned source/drain contact areas. The method employs the use of a stacked gate electrode layer having a tetra-ethyl-ortho-silicate (TEOS) oxide and a hard mask of silicon nitride on the gate electrode polysilicon layer. This stacked gate structure is used during patterning and prevents a buildup of polymer on the sidewall. The end result is improved gate line length tolerance, improved gate sidewall spacers, that minimize shorts between metal source/drain contacts and the polysilicon gate electrodes.
U.S. Pat. No. 5,480,814 entitled xe2x80x9cProcess of Making a Polysilicon Barrier Layer in a Self-Aligned Contact Modulexe2x80x9d granted Jan. 2, 1996 to Wuu et al shows a method of forming a metal contact in a self aligned contact region over an impurity region in a substrate. A doped polysilicon layer is formed over the device surface except in a contact area. A thin polysilicon barrier layer and a metal layer are then formed over the poly layer and the contact area. The resulting metal contact structures are reported to have superior step coverage, lower resistivity, and maintains the shallow junction depth of buried impurity regions.
The present invention is directed to a novel method of forming self aligned metal electrical contacts to source/drain areas allowing for xe2x80x9czeroxe2x80x9d spacing between the contact and gate area and a summary of the main embodiments of the present invention follows.
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which the fabrication of self aligned metal contacts to source/drain area is described, in the manufacture of CMOS MOSFET devices. As a background to the present invention, reference is first made to conventional Prior Art methods.
The standard or conventional Prior Art method for fabricating metal self-aligned contact to source/drain area consists of the follow process steps. Provided are the following layers and structures comprising: substrate of single crystal silicon semiconductor, source/drain contact region over source/drain ion implantation/diffusion area, FET gate oxide, gate electrode stack which consists of insulator capped polycide structure (gate oxide, polysilicon gate, and metal silicide). The gate insulator cap material is referred to as the hard mask insulator layer. Gate etch over the gate region is needed to remove this hard mask insulator layer (cap) prior to an etch step which etches into the polycide structure. After a conventional gate sidewall spacer formation process and source/drain ion implantation, another insulator layer, typically silicon nitride, is used to serve as the etch-stop layer for the self aligned contact (SAC) etch process when the cap insulator used is a silicon oxide layer (BPSG, boro phosphosilicate glass). The SAC etch process to contact the source/drain area removes the BPSG and stops either on the etch-stop insulator or on the gate hard mask layer. Then, a second etch step with different chemistry is utilized, in the case where an etch-stop layer is utilized, to remove the etch-stop layer. In this standard or conventional SAC process, an additional gate contact patterning mask is needed to open the contacts to the gate electrode, over the polysilicon gate.
One of the first embodiments of the present invention for fabricating metal self-aligned contact to the source/drain area is described below. For completeness, the following layers are provided comprising: the substrate of single crystal silicon, gate oxide, polysilicon gate with appropriate gate sidewall spacers. Key to this invention is the use of a special chemical vapor deposition (CVD) process that produces a non-conformal layer of silicon nitride over the gate. This special chemical vapor deposition (CVD) process, fabricating the said non-conformal layer of silicon nitride, simplifies this SAC process to source/drain areas and eliminates the need for an etch-stop layer, which was required earlier in the Prior Art conventional processing. As can be analyzed using cross-sectional specimens with SEM microscopy, the non-conforming silicon nitride layer is much thicker over the top of the polysilicon gates, than is said nitride at the bottom and in between the polysilicon gates. This special non-conformal chemical vapor deposition (CVD) silicon nitride layer, as described above, is a key embodiment to this invention, SAC to source/drain method or process.
A more specific object of the present invention is to provide an improved method of forming an integrated circuit in which the self aligned contact source/drain process is simplified and designed to fabricate more reliable devices. Using SEM microscopy to aid in process analysis, the.results of special chemical vapor deposition (CVD) conditions for both a silicon dioxide layer and a silicon nitride layer over closely spaces polysilicon gate structures were analyzed. These non-conformal layers (data taken from a current manufacturing CMOS production process) over polysilicon gates, further enhance some of the main elements and embodiments of the present invention. In addition, by this method the use of a hard mask layer on top of the gate is eliminated by using the said non-conformal deposition of chemical vapor deposition of silicon nitride. One of the process problems of depositing a chemical vapor deposition (CVD) layer of film between two closely structures, i.e., polysilicon gates, is known as xe2x80x9cbread loafingxe2x80x9d, a film layer appears to have a cross-sectional profile of a loaf of bread at the top edge and in between poly gates. Too much xe2x80x9cbread loafingxe2x80x9d can cause the chemical vapor deposition (CVD) process to fail to deposit adequate film between the poly gate structures. Furthermore, the chemical vapor non-conformal deposition processes can produce different thickness between the top and bottom of the dense, closely spaced poly lines. However, a chemical vapor deposition rate ratio of 3:1, between the top and bottom of poly, is achievable by fine tuning.the chemical vapor deposition process.
In one of the key embodiments of the present invention, self aligned contact process to source/drain area, the non-conformal chemical vapor deposition (CVD) of silicon nitride film layer on and in between polysilicon gate structures, has the following properties: non-conformal chemical vapor deposition rate is set at least a 3 to 1 ratio, deposition on top of poly gate being 3xc3x97 to deposition in between and at the bottom of poly gates being 1xc3x97. Therefore, a consist silicon nitride film thickness of 3xc3x97 is achieved on the top of the poly gates, while a silicon nitride film thickness of 1xc3x97 is achieved next to and in between gate structures. These stated desirable results have been achieved by this process with a special fine tuning of the non-conformal chemical vapor deposition (CVD) process conditions.
And in yet another key embodiment of the present invention, self aligned contact process to source/drain area, results are presented from an actual state of-the-art CMOS process using the SAC process from this invention. These results are from SEM analysis of the non-conformal deposition processes for: chemical vapor deposition of silicon nitride and silicon dioxide films, respectively. Test results of deposited film thickness (on top poly gates and at the bottom in between poly gates) indicate that favorable thickness ratios between top and bottom of 2:1 for the chemical vapor deposited (CVD) layer of silicon dioxide, and for the chemical vapor deposited (CVD) layer of silicon nitride of 3:1, can be achieved by the process methods of this invention. These thickness ratios achieved are beneficial and desirable for device fabrication for several reasons, that are: ease and simplification of processing, improvement of round rule designs and improvement in device reliability.
And in yet another aspect to the main embodiments of the present invention, self aligned contact process to source/drain area, several key processing features are described in this section for contact to actual device structures. A non-conformal chemical vapor deposition (CVD) silicon nitride is deposited between two parallel polysilicon lines. Through standard conventional processing, several other layers of film are provided, comprising of: gate sidewall spacers, a thick layer of BPSG boro phosphosilicate glass, silicon source/drain region. To open self aligned contacts (SAC) between these two poly lines, a twofold etch process is followed. Firstly, the BPSG boro phosphosilicate glass is removed by etching and the etch step is stopped on chemical vapor deposition (CVD) silicon nitride layer. Note, the selective etch just described must have a high selectivity to etch the silicate glass and not the nitride layer. Secondly, the etch chemistry is changed to remove the remaining silicon nitride on top of the silicon source/drain region by a making use of a time controlled etching process. The key point to note, by using the process method this invention, is that the non-conformal silicon nitride on the top of the poly is much thicker, than the nitride on the surface of silicon (source/drain region) between two parallel poly lines. Hence, the second etch step, described above, can be well controlled to remove just the silicon nitride on the bottom, while safely keeping more than sufficient silicon nitride on top of the poly for isolation purposes. Hence, this process method describe in this invention has good built-in advanced process controls.
In another aspect of this invention, the said non-conformal chemical vapor deposition (CVD) film properties and deposition profiles, key to this invention, are dependent on the chemical vapor deposition (CVD) conditions and advanced process controls. Therefore, in order to make proper and effective use of the non-conformal deposited silicon nitride film layer in the self aligned contact (SAC) process, the deposition process must be well characterized and well controlled. Several useful formulas are given and described in detail in the xe2x80x9cDescription of the Preferred Embodimentsxe2x80x9d section. These formulas provide helpful information to be used with film profiles to feedback to the chemical vapor deposition (CVD), non-conformal film processing conditions for process optimization. Some of the other considerations for process optimization are: poly to poly line and gate spacing, which is important, as well as, the degree of non-conformally of the silicon nitride film, the design ground rules for poly to poly and source/drain contact space, and process problems such as xe2x80x9cbread loafingxe2x80x9d. Other factors, i.e., the selectivity of the etch between BPSG boro phosphosilicate glass and the silicon nitride layer are also important. For the requirement of contact to poly isolation and to maintain good electrical isolation, the top corner process thickness of the non-conformal, chemical vapor deposition (CVD) silicon nitride is dependent on: (1) chemical vapor deposition (CVD) conditions (2) poly thickness and spacing (3) etch selectivity between BPSG, boro phosphosilicate glass and silicon nitride.
And yet in another application of this invention, the above an other objectives are realized by applying this invention to chip device areas where the poly to poly lines and gate distances are large. The non-conformal, chemical vapor deposition (CVD) silicon nitride process is dependent on the pattern density of the substrate. Thus, this self aligned contact scheme can only be made between two adjacent parallel poly lines, with fixed poly to poly spacing design rules. Furthermore, in the wider poly spacing areas, the silicon nitride thickness on the silicon will be the same as on top of poly and hence, the SAC process is no longer valid. In addition, of another concern are the connections from metal to poly, where there is a concern with the thick silicon nitride layer on top of poly. These two concerns that were raised above can be easily solved by separating the SAC patterning mask from the normal contact masks. Thusly, the normal or standard contact mask can be used for both the poly contacts and diffusion contacts on or in an xe2x80x9copen areaxe2x80x9d, large distances or spaces.
And in yet another embodiment of this invention, self aligned contact process to source/drain area, is the enhanced electrical device performance yielded by the application of this invention to CMOS MOSFET""s. The electrical performance of the invented SAC process is determined by the.effective width of the contact to the source/drain and by some other parameters. The larger the effective contact width to the source/drain, the lower the contact electrical resistance. This invention gives a process that is self aligned, which minimizes design contact area (xe2x80x9czeroxe2x80x9d design ground rule tolerance, spacing from contact to gate), while maximizing contact area for metal to source/drain, effective contact width.
In summary, the many of the embodiments and features of the present invention for fabricating metal self-aligned contact to the source/drain area were described. However, there are other standard processes and process steps that take place in the fabrication of circuits, and more specifically CMOS MOSFET""s, that are not specifically stated, referenced or described herein. However, those who are skilled in the art can provide these elements.